1. Field of the Invention
The invention relates to time-shared bus computer architecture having bus Users with private cache storage, particularly with respect to bus access by Users during cache consistency procedures.
2. Description of the Prior Art
Present day digital computers often utilize a time-shared bus architecture including plural bus Users with one or more Users having a private cache. This architecture typically includes an I/O module User, one or more processor Users and a main memory User. An arbiter on the bus traditionally arbitrates the bus requests from the Users and the bus grants thereto. In operation, a User with a cache copies words from main memory into its cache and performs processes using the words in cache. For example, a processor User may copy program instructions and data from main memory to its cache and, thereafter, execute the program task from cache. As is appreciated, cache is used in this manner to enhance performance. The processor User with the cache avoids going back and forth on the bus to main memory for each instruction.
While a first User is performing processes with its cache, a second User may write to main memory in the locations copied by the first User into its private cache, rendering the cached words from the overwritten locations invalid. In order to maintain cache consistency, the first User monitors the bus and when a write to memory is detected from the second User, the first User executes a cache cycle to determine if it has data from the write-addressed main memory location. If so, the first User invalidates its cache so that the invalid data is not subsequently used. Typically, the execution time of a cache cycle occupies a significant number of bus cycles. Thus, while a cache cycle is executing, the second User, or a third User, can put another request on the bus to do another memory write while the first User is occupied with the original memory write.
In a particular design initially tried by the present inventors in the development of a computer system utilizing the above described architecture, the first User put a RETRY signal on the bus advising the second/third User to retry its memory write request at a later time and the second/third User included a Retry mechanism that retried the bus request at a fixed time interval after receiving the RETRY signal. Additionally, the User Retry mechanism included logic to establish a limit on the number of sequential retries that could be attempted before a decision was made that a malfunction had occurred. When such a malfunction was detected, the process was aborted and an error message generated.
The present inventors discovered that, although a User may indicate a Retry-Limit-Exceeded error condition, the condition was not caused by a malfunction. Instead, a rarely occurring synchronism between repetitive WRITES TO MEMORY by a first bus User, the concomitant cache cycles of a second bus User and the Retry mechanism in a third bus User, resulted in the apparent "failure" of the third bus User. The third bus User was forced to retry its bus operation beyond its Retry Limit. This failure mechanism, herein denoted as bus lockout, will be described later in greater detail.
The occurrence of bus lockout may be exacerbated since the sending of the RETRY signal is repeated when numerous bus Users attempt WRITES TO MEMORY via the bus during a cache cycle. Furthermore, each of numerous bus Users can have a cache, thus causing numerous RETRY signals to be sent.
In the non-analogous technology of Local Area Networks (LAN), communication users on the LAN retry transmissions using a randomly selected Retry wait interval. Such a system is described in U.S. Pat. No. 4,410,889, issued Oct. 18, 1983. It is appreciated that the random Retry wait interval is unsuitable for use in the computer architecture described above. A randomly selected Retry wait interval can be unacceptably long, seriously degrading the performance of the User.